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2-mbit (128k x 16) static ram cy62137ev30 mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05443 rev. *b revised february 14, 2006 features ? very high speed: 45 ns ? wide voltage range: 2.20v?3.60v ? pin-compatible with cy62137cv30 ? ultra-low standby power ? typical standby current: 1 a ? maximum standby current: 7 a ? ultra-low active power ? typical active current: 2 ma @ f = 1 mhz ? easy memory expansion with ce , and oe features ? automatic power-down when deselected ? cmos for optimum speed/power ? byte power-down feature ? offered in pb-free 48-ball vfbga and 44-pin tsopii package functional description [1] the cy62137ev30 is a high-performance cmos static ram organized as 128k words by 16 bits. this device features ad- vanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-down featur e that significantly reduces power consumption by 90% when addresses are not toggling. the device can also be put into standby mode reducing power consumption by more than 99% when deselected (ce high or both ble and bhe are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce high), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce low and we low). writing to the device is accomplished by asserting chip en- able (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the locati on specified on the address pins (a 0 through a 16 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by asserting chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. the cy62137ev30 is available in 48-ball vfbga and 44-pin tsopii packages. note: 1. for best practice recommendations, please refer to the cypres s application note ?system design guidelines? on http://www.cypr ess.com. l og i c bl oc k di agram 128k x 16 ram array i/o 0 ? i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ? i/o 15 ce we bhe a 16 a 0 a 1 a 9 power - down circuit bhe ble ce a 10 ble [+] feedback [+] feedback
cy62137ev30 mobl ? document #: 38-05443 rev. *b page 2 of 12 pin configurations [2, 3] vfbga (top view) 44 tsop ii (top view) product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1mhz f = f max min. typ. [7] max. typ. [7] max. typ. [7] max. typ. [7] max. cy62137ev30-45ll 2.2v 3.0v 3.6v 45 ns 2 2.5 15 20 1 7 note: 2. nc pins are not connected on the die. 3. pins d3, h1, g2, and h6 in the bga package are address exp ansion pins for 4 mb, 8 mb, 16 mb, and 32 mb, respectively. we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe nc nc a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h a 16 nc vcc we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 v cc a 16 a 15 a 14 a 13 a 4 a 3 oe v ss a 5 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe a 1 a 0 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 v ss i/o 6 i/o 4 i/o 5 i/o 7 a 6 a 7 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 8 a 9 a 10 a 11 a 12 nc nc [+] feedback [+] feedback
cy62137ev30 mobl ? document #: 38-05443 rev. *b page 3 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ..... ?65c to + 150c ambient temperature with power applied .......... .............. .............. ..... ?55c to + 125c supply voltage to ground potential ............................. ?0.3v to 3.9v (v cc(max) + 0.3v) dc voltage applied to outputs in high-z state [4, 5] ............... ?0.3v to 3.9v (v cc max + 0.3v) dc input voltage [4, 5] ........... ?0.3v to 3.9v (v cc max + 0.3v) output current into outputs (low) ............................ 20 ma static discharge voltage ........ ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range device range ambient temperature v cc [6] cy62137ev30-45ll industrial ?40 c to +85c 2.2v to 3.6v electrical characteristics over the operating range parameter description test conditions 45 ns unit min. typ. [7] max. v oh output high voltage i oh = ?0.1 ma v cc = 2.20v 2.0 v i oh = ?1.0 ma v cc = 2.70v 2.4 v v ol output low voltage i ol = 0.1 ma v cc = 2.20v 0.4 v i ol = 2.1ma v cc = 2.70v 0.4 v v ih input high voltage v cc = 2.2v to 2.7v 1.8 v cc + 0.3 v v cc = 2.7v to 3.6v 2.2 v cc + 0.3 v v il input low voltage v cc = 2.2v to 2.7v ?0.3 0.6 v v cc = 2.7v to 3.6v ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels 15 20 ma f = 1 mhz 2.0 2.5 i sb1 automatic ce power-down current ? cmos inputs ce 1 > v cc ? 0.2v, ce 2 < 0.2v v in > v cc ? 0.2v, v in < 0.2v) f = f max (address and data only), f = 0 (oe and we ), v cc = 3.60v 17 a i sb2 automatic ce power-down current ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.60v 17 a notes: 4. v il(min.) = ?2.0v for pulse durations less than 20 ns. 5. v ih(max) =v cc +0.75v for pulse durations less than 20ns. 6. full device ac operation assumes a 100 s ramp time from 0 to vcc(min) and 200 s wait time after v cc stabilization. 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c. [+] feedback [+] feedback
cy62137ev30 mobl ? document #: 38-05443 rev. *b page 4 of 12 capacitance (for all packages) [8] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter description test conditions bga tsop ii unit ja thermal resistance (junction to ambient) [8] still air, soldered on a 3 4.5 inch, two-layer printed circuit board 75 77 c/w jc thermal resistance (junction to case) [8] 10 13 c/w ac test loads and waveforms parameters 2.50v 3.0v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min. typ. [7] max. unit v dr v cc for data retention 1 v i ccdr data retention current v cc = 1v ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v 0.8 3 a t cdr [8] chip deselect to data retention time 0ns t r [9] operation recovery time t rc ns v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thvenin equivalent all input pulses r th r1 data retention waveform [10] notes: 8. tested initially and after any design or proc ess changes that may affect these parameters. 9. full device operation requires linear v cc ramp from v dr to v cc(min.) > 100 s or stable at v cc(min.) > 100 s. v cc(min) v cc(min) t cdr v dr > 1.5v data retention mode t r v cc ce or bhe .ble [+] feedback [+] feedback
cy62137ev30 mobl ? document #: 38-05443 rev. *b page 5 of 12 switching characteristics over the operating range [11] parameter description 45 ns unit min. max. read cycle t rc read cycle time 45 ns t aa address to data valid 45 ns t oha data hold from address change 10 ns t ace ce low to data valid 45 ns t doe oe low to data valid 22 ns t lzoe oe low to low z [12] 5ns t hzoe oe high to high z [12, 13] 18 ns t lzce ce low to low z [12] 10 ns t hzce ce high to high z [12, 13] 18 ns t pu ce low to power-up 0 ns t pd ce high to power-down 45 ns t dbe ble /bhe low to data valid 45 ns t lzbe ble /bhe low to low z [12] 5ns t hzbe ble /bhe high to high z [12, 13] 18 ns write cycle [14] t wc write cycle time 45 ns t sce ce low to write end 35 ns t aw address set-up to write end 35 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 35 ns t bw ble /bhe low to write end 35 ns t sd data set-up to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high-z [12, 13] 18 ns t lzwe we high to low-z [12] 10 ns notes: 10. bhe .ble is the and of both bhe and ble . the chip can be deselected by either disabling the chip enable signals or by disabling both bhe and ble . 11. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns (1v/ns) or less, ti ming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 12. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 13. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high- impedance state. 14. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edg e of the signal that terminates the write. [+] feedback [+] feedback
cy62137ev30 mobl ? document #: 38-05443 rev. *b page 6 of 12 switching waveforms read cycle 1 (address transition controlled) [15, 16] read cycle no. 2 (oe controlled) [16, 17] notes: 15. the device is contin uously selected. oe , ce = v il , bhe and/or ble = v il . 16. we is high for read cycle. 17. address valid prior to or coincident with ce and bhe , ble transition low. address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t lzbe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high v cc supply current t hzbe bhe /ble t lzoe address t dbe t doe [+] feedback [+] feedback
cy62137ev30 mobl ? document #: 38-05443 rev. *b page 7 of 12 write cycle no. 1 (we controlled) [14, 18, 19] write cycle no. 2 (ce controlled) [14, 18, 19] notes: 18. data i/o is high impedance if oe = v ih . 19. if ce goes high simultaneously with we = v ih , the output remains in a high-impedance state. 20. during this period, the i/os are in output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe data in note 20 bhe /ble t bw t sce t hd t sd t pwe t ha t aw t sce t wc t hzoe data in ce address we data i/o oe note 20 bhe /ble t bw t sa [+] feedback [+] feedback
cy62137ev30 mobl ? document #: 38-05443 rev. *b page 8 of 12 write cycle no. 3 (we controlled, oe low) [19] write cycle no. 4 (bhe /ble controlled, oe low) [19] switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 20 t bw bhe /ble data i/o address t sd t sa t ha t aw t wc ce we data in note 20 t bw bhe /ble t sce t pwe t hzwe t hd t lzwe [+] feedback [+] feedback
cy62137ev30 mobl ? document #: 38-05443 rev. *b page 9 of 12 truth table ce we oe bhe ble inputs/outputs mode power h x x x x high z deselect/power-down standby (i sb ) x x x h h high z deselect/power-down standby (i sb ) l h l l l data out (i/o o ?i/o 15 ) read active (i cc ) l h l h l data out (i/o o ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) l h h l l high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l h high z output disabled active (i cc ) l l x l l data in (i/o o ?i/o 15 ) write active (i cc ) l l x h l data in (i/o o ?i/o 7 ); i/o 8 ?i/o 15 in high z write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 45 CY62137EV30LL-45BVXI 51-85150 48-ball very fine pitch bga (6 mm 8mm 1 mm) (pb-free) industrial 45 cy62137ev30ll-45zsxi 51-85087 44-pin tsop ii (pb-free) [+] feedback [+] feedback
cy62137ev30 mobl ? document #: 38-05443 rev. *b page 10 of 12 package diagrams a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 48-pin vfbga (6 x 8 x 1 mm) (51-85150) 51-85150-*d [+] feedback [+] feedback
cy62137ev30 mobl ? document #: 38-05443 rev. *b page 11 of 12 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. mobl is a registered trademark, and more battery life is a trademark, of cypress semicond uctor. all product and company names mentioned in this document may be t he trademarks of their respective holders. package diagrams (continued) 44-pin tsop ii (51-85087) 51-85087-*a [+] feedback [+] feedback
cy62137ev30 mobl ? document #: 38-05443 rev. *b page 12 of 12 document history page document title: cy62137ev30 mobl ? 2-mbit (128k x 16) static ram document number: 38-05443 rev. ecn no. issue date orig. of change description of change ** 203720 see ecn aju new data sheet *a 234196 see ecn aju changed i cc max at f=1mhz from 1.7 ma to 2.0 ma changed i cc typ from 12 ma (35 ns speed bin) and 10 ma (45 ns speed bin) to 15 ma and 12 ma respectively changed i cc max from 20 ma (35 ns speed bin) and 15 ma (45 ns speed bin) to 25 ma and 20 ma respectively changed i sb1 and i sb2 typ from 0.6 a to 0.7 a changed i sb1 and i sb2 max from 1.5 a to 2.5 a changed i ccdr from 1 a to 2 a fixed typos on tsop ii pinout: pin 18-22: address lines pin 23: nc added pb-free information *b 427817 see ecn nxr converted from advanced information to final. removed 35 ns speed bin removed ?l? version changed ball e3 from dnu to nc. removed the redundant footnote on dnu. moved product portfolio from page # 3 to page #2. changed i cc (max) value from 2 ma to 2.5 ma and i cc (typ) value from 1.5 ma to 2 ma at f=1 mhz changed i cc (typ) value from 12 ma to 15 ma at f = f max =1/t rc changed i sb1 and i sb2 typ. values from 0.7 a to 1 a and max. values from 2.5 a to 7 a. changed v cc stabilization time in footnote #7 from 100 s to 200 s changed the ac test load capacitance from 50pf to 30pf on page# 4 changed v dr from 1.5v to 1v on page# 4. changed i ccdr from 2 a to 3 a. added i ccdr typical value. corrected t r in data retention characteristics from 100 s to t rc ns changed t oha , t lzce and t lzwe from 6 ns to 10 ns changed t lzbe from 6 ns to 5 ns changed t lzoe from 3 ns to 5 ns changed t hzoe, t hzce, t hzbe and t hzwe from 15 ns to 18 ns changed t sce, t aw and t bw from 40 ns to 35 ns changed t pwe from 30 ns to 35 ns changed t sd from 20 ns to 25 ns updated the ordering information table and replaced the package name column with package diagram. [+] feedback [+] feedback

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